Difference between revisions of "ATtiny84 PWM"

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Latest revision as of 13:53, 1 February 2016



	// Example #1  PWM on pin PB2 (OC0A which is on 8-bit timer0)
	// For 8MHz clock: 61.2kHz period (16.25ms) of which half is on and half is off
	DDRB = 1<<DDB2;       // make OC0A (DDB2) PWM output pin	
	TCCR0A = (1<<COM0A1) | (1<<COM0B0) | (1<<WGM00);  // Clear OC0A/OC0B on Compare Match (bit 7 + 6)
							    // PWM, Phase Correct
	TCCR0B = (1<<CS02);   // clkI/O/256(from prescaler)
	// not used // TIMSK1=0B00000010;    //enable output compare interrupt for OCR1A
	OCR0A = 127;          // set 50% duty cycle (0.5*256)


	// Example #2  PWM on pin PA6 (OC1A which is on 16-bit Timer1)
	// For 8MHz clock: 61.2kHz period (16.25ms) of which half is on and half is off
	DDRA = 1<<DDA6;       // make OC1A (DDA6) PWM output pin	
	TCCR1A = (1<<COM1A1) | (1<<COM1B0) | (1<<WGM00);  // Clear OC1A/OC1B on Compare Match (bit 7 + 6)
							  // PWM, Phase Correct
	TCCR1B = (1<<CS02);   // 256 prescaler
	OCR1A = 127;          // set 50% duty cycle (0.5*256)


See also: